1. Technical Field
This invention relates to testing of integrated circuit logic chips and more particularly to oscillation prevention during the testing thereof.
Integrated circuit logic chips are widely employed in data processing and other electronic systems. An integrated circuit logic chip typically includes a plurality of on-chip receivers for receiving binary input signals, a plurality of off-chip drivers for transmitting binary output signals, and a logic gate netwrok. The logic gates are connected between the on-chip receivers and off-chip drivers to produce binary output signals which are a predetermined logical function of the binary input signals. The logic chip also may include registers or latches for on-chip storage of intermediary signals. In the present state of the art up to sixty or more on-chip receivers and up to sixty or more off-chip drivers as well as thousands of logic gates may be integrated in a semiconductor logic chip.
Logic chips are typically tested in a logic tester. The tester typically includes a plurality of drivers for producing input signals for the logic chip and a plurality of receivers for receiving the logic chip output signals. The tester drivers and receivers are electrically connected to the chip receivers and drivers, respectively, by means of a test fixture which permits rapid chip insertion and withdrawal. The tester also typically includes means for producing various combinations of input signals for the chip under test and means for comparing the output signals produced by the chip under test with expected output signals. In order to fully test a complex logic chip, many combinations of input signals and expected output signals must be produced. The tester also typically performs parametric tests on the on-chip receivers and off-chip drivers. Parametric tests measure the electrical properties of the drivers or receivers, e.g., source and sink currents, voltage levels, and input or output impedances.
2. Background Art
As the complexity of logic chips and of the associated testers have increased, unwanted oscillation of the logic chip during testing has particularly become a problem. Unwanted oscillations often prevent the testing of a logic chip even though the logic chip is perfectly operational when placed in its intended environment.
Unwanted logic chip oscillation during testing arises when switching transients from the off-chip drivers are coupled back to the chip power supply busses through the unbypassed inductance of the test fixture. The tester itself typically includes bypass capacitors for filtering transient noise within the tester. However, the test fixture has a high inductance associated therewith. This inductance is not bypassed by the tester bypass capacitors. Accordingly, the power supply inductance seen by the chip during testing is much higher than would be typical in the intended environment.
During testing, when an off-chip driver switches binary state, the transmission line connecting the off-chip driver to the tester must be discharged. The discharge path is through the driver, and through the unbypassed inductance of the test fixture. The discharge current from the driver causes a voltage spike on the chip power supply busses, proportional to the rate of change of the current and the number of drivers switching. The noise pulse on the power supply busses is imposed on all of the logic chip circuits which are powered therefrom.
This switching noise, commonly called ".DELTA.I noise" may cause the logic chip to change state or oscillate. The logic chip changes state when an input receiver or logic gate is disturbed and causes an off-chip driver to switch. Oscillation occurs when off-chip driver switching creates a new noise spike which in turn distrubs an input receiver or a gate and again causes the off-chip driver to change state. This oscillation continues in an uncontrollable manner.
As described above, the probability of logic state switching and chip oscillation is directly proportional to the switching speed of the off-chip drivers, the number of drivers which simultaneously switch and the unbypassed tester inductance. Logic state switching and oscillation typically manifest themselves at three time points during logic chip testing. First, when power is initially applied to the chip after it has been placed in the test fixture, a number of off-chip drivers may switch at once and thereby cause the chip to oscillate. In fact, it will be shown below that for logic chips fabricated in high speed current switch technology, all of the off-chip drivers may simutaneously switch upon application of power to the chip, to thereby cause oscillation. After initial power-on, parametric voltage level tests performed on a single on-chip receiver may cause many or all of the off-chip drivers to simultaneously switch state, thereby causing oscillations. Finally, the input pattern tests may also cause simultaneous switching of large numbers of off-chip drivers to produce oscillation. Oscillation at any point in the testing sequence precludes testing of the chip.
Since the probability of oscillation is directly proportional to the unbypassed tester inductance, the switching speed of the off-chip drivers and the number of drivers which simultaneously switch, the oscillation prolem could be solved by imposing design constraints on these parameters. For example, number of output drivers which can simultaneously switch and the switching speed of a driver can be intentionally limited by the chip designer. However, such design constraints would impose undue limitations on logic chip performance to compensate for a problem which does not occur outside of the testing environment.